Committees

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 Session Numbers
1A Beyond Printing Single
1B Memory and Delay Test
1C Manufacturing-Aware Optimizing Power, Performance and Reliability of the Memory Hierarchy of Embedded Systems
1P 2020 Vision: What the Recent History of EDA will Look Like in Nine Years
1S The ABCs of Formal Verification: Models, Algorithms, and Methodologies in RTL- and ESL-based Design Flows
1T GPU Programming for EDA with OpenCL
1W IEEE/ACM Workshop on Variability Modeling and Characterization
2A Placement and Clocking
2B Recent Advances in Behavioral Modeling and Timing Analysis
2C Caches and Parallel Embedded Software
2P Manycore, Heterogeneous, or Neither: Which one is the way to go for EDA?
2S The Role of EDA in Digital Print Automation and Infrastructure Optimization
2T Nano-Electro-Mechanical Relay Integrated Circuits and Technology
2W International Workshop on Adaptive Power Management with Machine Intelligence
3A DFM: From Test Structures to Computation
3B High-Level and Sequential Synthesis
3C Addressing the Physical Challenges of NoC Design
3S Emerging Technologies: The Next Logic Switch
3T Emerging Nonvolatile Memory and Memristors
3W Seventh International Workshop on Constraints in Formal Verification (CFV'11)
4A Advances in Global Routing
4B Analog/Mixed-Signal Design Challenges: Temperature, Verification and the Human Factor
4S The Future of Clock Network Synthesis
4W Nanolithography & IC Design/CAD in Extreme Scaling: What, Why, and How?
5A Routing Optimization Techniques
5B Let’s Gap Together! Urgent ToDo’s for EDA from Industry Point of View
5C System Level Modeling for Early Design Space Exploration, Simulation, and Synthesis
5S Brain-Inspired Architectures: Abstractions to Accelerators
6A Modeling of Devices and Analog Systems
6B Logic Level Synthesis
6C Robustness and Variability
6D CAD for Bio/Nano/Post-CMOS Systems
6S 2011 TAU Power Grid Simulation Contest
7A Analog Circuit Sizing and Layout Optimization
7B Modeling and Simulation of Interconnect and Power Networks
7C Stress, Electromigration, and Soft Error Mitigation
8B Advances in Debugging and Simulation
8C System-level Power Management
9A Advances in Clocking and Routing for ASIC and On-Chip Communication
9B Frontiers in Verification
9C System-level Power and Thermal Estimation
10A Advanced Timing and Power Optimizations in Physical Design
10B Test Cost and Quality
10C New Techniques for System-level Communication Synthesis and Hardware Metering