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 Session Numbers
1A Sensing and Harvesting for Energy-Efficient System Design
1B Test Cost and Security
1C DFM for EUV and Multiple Patterning Lithography
1D Algorithms for Analysis and Optimization of Future Cyber Physical Systems
1W International Workshop on Design Automation for Analog and Mixed-Signal Circuits
2A Hardware and Software Techniques for Memory Hierarchy Optimization
2B Simulation-Based Verification
2C Advanced Topics in Routing
2D Computing in the Random Noise: The Bad, the Good, and the Amazing Grace
2W 1st International Workshop on Domain-Specific Multicore Computing (DSMC)
3A Timing and Behavioral Modeling
3B Formal Approaches to Verification
3C Leakage and Technology-Aware Gate Sizing
3D Dealing with Manufacturing and Reliability in Extremely Scaled CMOS and Beyond
3W IEEE Workshop on Variability Modeling and Characterization (VMC)
4A System-Level Modeling and Optimization of Power Ground Networks
4B Challenges in 3-D IC Technologies and Integration
4C Placement for the Next Decade
4D Automation of Biological System Modeling and Analysis
4W 2012 IEEE/ACM Workshop on CAD for Multi-Synchronous and Asynchronous Circuits and Systems
5A Power-Aware Architecture and System Design
5B Reliability and Thermal Issues in 3-D ICs
5C CAD Contest
5D Power Characterization and Optimization in Smartphones
5W International Workshop on Hardware/Software Techniques for Cross-Layer Resiliency
6A Computational Approaches for Biological Systems
6B Fast Parallel Power Ground Network Simulation Methods
6C Efficient Verification and Yield Estimation for Analog Circuits
6D Toward Co-Design in High-Performance Computing Systems
7A System-Level Modeling and Optimization
7B High-Level Design Methods
7C The Next Wave: Top Challenges in Electromagnetic-Based Design Automation
7D Printable Electronics
8A Runtime Adaptation for Performance and Reliability
8B Challenges in Embedded CPU/GPU Core Design
8C Emerging Technologies for More-Moore and More-than-Moore Eras
8D The Secret Art of Analog/Mixed-Signal Post-Silicon Validation
9A Novel Techniques for Network on Chips and Hardware Security
9B Advances in Logic Synthesis
9C New Approaches in Physical Synthesis of Nano-Scale Analog Circuits
9D Power Grid Simulation and Verification for Billion-Transistor VLSI Designs
10A Power-Efficient Design and Management of OLED Displays
10B 2-D and 3-D Physical Design Optimization
10C Enabling Design for Resilience
10D High-Performance, Low-Power Resonant Clocking
120 The Empire Strikes Back or Attack of the Clones? The Once and Future CAD
400 The Limits of Parallelism for Simulation